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ISL8510
Pin Descriptions
In addition, the PWM regulator power-good and undervoltage
protection circuitry use FB_PWM to monitor the regulator
output voltage.
24
23
22
21
20
19
PHASE
FB_LDO 1
VOUT 2
18 VIN
17 VIN
Switch node connections to internal power MOSFET source,
external output inductor, and external diode cathode.
VIN_LDO 3
GND 4
GND 5
NC 6
25
GND
16 PHASE
15 PHASE
14 BOOT
13 PVCC
BOOT
Floating bootstrap supply pin for the power MOSFET gate
driver. The bootstrap capacitor provides the necessary
charge to turn and hold on the internal N-Channel MOSFET.
Connect an external capacitor from this pin to PHASE.
7
8
9
10
11
12
EN
PWM controller enable input. The PWM converter and
LDO's outputs are held off when the pin is pulled to ground.
When the voltage on this pin is logic high, the chip is
VIN
The input supply for the PWM regulator power stage and the
source for the internal linear regulator that provides bias for
the IC. Place a ceramic capacitor from VIN to GND close to
the IC for decoupling (typical 1μF).
PVCC
Connect this pin to VCC.
GND
Ground connect for the IC and thermal relief for the package.
The exposed pad must be connected to GND and soldered
to the PCB. All voltage levels are measured with respect to
this pin.
VCC
Internal 5V linear regulator output provides bias to all the
internal control logic. The ISL8510 may be powered directly
from a 5V (±10%) supply at this pin. When used as a 5V supply
input, this pin must be externally connected to VIN. The VCC
pin must always be decoupled to GND with a ceramic bypass
capacitor (minimum 1μF) located close to the pin.
TABLE 1. INPUT SUPPLY CONFIGURATION
enabled.
SS
Program pin for soft-start duration. A regulated 30μA pull-up
current source charges a capacitor connected from the pin to
GND. The output voltage of the converter follows the ramping
voltage on the SS pin.
VIN_LDO
Input voltage pin for LDO.
VOUT
LDO output pin. Bypass with a minimum of 2.2 μ F, low ESR
capacitor to GND for stable operation.
FB_LDO
Used to set the output of LDO with the proper selection of
resistor divider. The resistors should be selected to provide a
minimum current of 200nA load for the LDO.
CC
Compensation capacitor connection for LDO. Connect a
0.033μF capacitor from pin to ground.
EN_LDO
INPUT
PIN CONFIGURATION
The pin is threshold-sensitive enable input for the LDO. Held
5.5V to 25V Connect the input supply to the VIN pin only. The VCC pin
will provide a 5V output from the internal linear regulator.
low, this pin disables LDO.
PG_PWM
5V ±10%
Connect the input supply to the VIN and VCC pins.
PWM converter power-good output. Open drain logic output
FB _PWM AND COMP
The standard buck regulator employs a single voltage control
loop. FB_PWM is the negative input to the voltage loop error
amplifier. COMP is the output of the error amplifier. The output
voltage is set by an external resistor divider connected to
FB_PWM. With a properly selected divider, the output voltage
can be set to any voltage between the power rail (reduced by
converter losses) and the 0.6V reference. Connecting an AC
network across COMP and FB_PWM provides loop
compensation to the amplifier.
8
that is pulled to ground when the output voltage is outside
regulation limits. Connect a 100k Ω resistor from this pin to
VCC. Pin is low when the buck regulator output voltage is
not within 10% of the respective nominal voltage, or during
the soft-start interval. Pin is high impedance when the output
is within regulation.
PG_LDO
Combined LDO power--good output. Connect a 100k Ω resistor
from this pin to VCC.
FN6516.2
December 15, 2008
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